Course manual 2023/2024

Course content

This course builds on a basic knowledge of microprocessor architecture. It develops this with and emphasis on instruction-level and thread-level concurrency in (multi-core) microprocessor design as well as concurrency in memory systems. The topics that are covered include superscalar and VLIW processor architectures, instruction- and thread-level parallelism, memory hierarchy, distributed- and shared-memory parallel computers.

The course also provides an introduction into programming models and techniques for multi-core processors found in everyday laptops to large-scale server systems. Here, the focus will be on multithreaded programming models for shared address space systems, where we discuss both OpenMP compiler directives and Posix threads.

Study materials

Literature

  • John Hennessy and David Patterson,'Computer Architecture: a Quantitative Approach', Morgan Kaufmann, 4th ed. or later

Objectives

  • To understand the principles and design of modern multi-core microprocessors and their microarchitectures.
  • To understand how such processors can be deployed in systems targeted for different application fields, such a as embedded / edge systems-on-a-chip or parallel/distributed computing systems.
  • Building a simulation model of a cache-coherent multi-core system, with which cache behavior in such systems can be analyzed and evaluated.
  • To develop an understanding of how such multi-core processors can be programmed.

Teaching methods

  • Lecture
  • Computer lab session/practical training
  • Self-study

Learning activities

Activity

Hours

Hoorcollege

28

Laptopcollege

28

Self study

112

Total

168

(6 EC x 28 uur)

Attendance

Programme's requirements concerning attendance (TER-B):

  • In the case of a practical training, the student must attend at least 100% of the practical sessions. Should the student attend less than 100%, the student must repeat the practical training, or the Examinations Board may have one or more supplementary assignments issued.
  • In the case of a tutorial, the student must attend at least 100% of the tutorial sessions. Should the student attend less 100%, the student must repeat the tutorial, or the Examinations Board may have one or more supplementary assignments issued.

Additional requirements for this course:

Presence at the computer labs is not compulsory but highly recommended.

Assessment

Item and weight Details

Final grade

50%

Computer Lab Assignments

Must be ≥ 5

50%

Theory Assignments

Must be ≥ 5

Inspection of assessed work

Contact your supervisor to make an appointment for inspection.

Fraud and plagiarism

The 'Regulations governing fraud and plagiarism for UvA students' applies to this course. This will be monitored carefully. Upon suspicion of fraud or plagiarism the Examinations Board of the programme will be informed. For the 'Regulations governing fraud and plagiarism for UvA students' see: www.student.uva.nl

Course structure

Weeknummer Onderwerpen Studiestof
1 Memory hierachy Ch. 2 + Appendix B
2 Memory consistency + cache coherence + start of processor micro-architectures Ch. 5 + Ch. 3 + Appendix C
3 Processor micro-architectures Ch. 3
4 Embedded processors + DSE for embedded systems Appendix E+H
5 OpenMP + start Pthreads  
6 Pthreads + HW multithreading + busses/crossbars Ch. 5 + Appendix F
7 no lectures (focus on paper review + lab assignments)  
8 no lectures (focus on paper review + lab assignments)  

Additional information

Prior knowledge: Students need to have programming skills in C/C++, and basic knowledge on computer organization.

Contact information

Coordinator

  • prof. dr. A.D. Pimentel